1. Field of the Invention
The present invention relates to a processing apparatus comprising a CPU executing a program, an internal circuit having an internal memory storing internal programs, and an external memory storing external programs, an integrated circuit wherein the CPU and the internal memory are integrated on one chip and the external memory can be provided exteriorly of the integrated circuit, and an integrated circuit package to which the chip on which such an integrated circuit is mounted, is molded.
2. Description of the Related Art
With the recent development of LSI technique, a CPU executing programs, a memory in which the programs executed by the CPU are stored and other various functional modules can be integrated on one chip, which contributes greatly to making an apparatus small in size, cost reduction and the like. To manufacture such an LSI, a memory storing programs may be mounted on an LSI chip in case of a system which executes the same program irrespectively of users and which does not need to change programs after completion. However, if it is necessary to execute different programs according to users or to change a program while the program is in use, then it is desirable to constitute an LSI so that an external memory can be further provided exteriorly of the LSI having the above constitution and to store programs which may be possibly changed while in use or programs which differ according to users in the external memory.
Meanwhile, in case of the system capable of adding the above-stated external memory exteriorly of the LSI, there is a probability that the content of the external memory is illicitly rewritten (programmed) or the external memory is replaced by a memory storing an illicit program and having the same specification as that of the external memory, with the result that important programs or data stored in the internal memory are illicitly accessed and the contents of the programs or data are illicitly interpreted. The following is one example of this case.
Recently, IC cards and magnetic cards each having a cash value or a point value corresponding to a cash as data is spreading increasingly. Following this, data protection becomes considerably significant so as to prevent the fabrication or falsification of cards. To do so, as shown in, for example, Japanese Patent Application Laid-Open No. 2916338, the protection of a card itself from being accessed is proposed. However, the write and read of card data are conducted through a card processing apparatus. Due to this, if the card processing apparatus illicitly interprets data or a program, the protection of a card itself becomes imperfect even if such protection is made.
The above-stated system in which an external memory is provided exteriorly is also desired as a card processing apparatus. The problem with the system is how to prevent illicit access.
The present invention has been made in view of the above circumstances. It is, therefore, an object of the present invention to provide a processing apparatus, an integrated circuit and an integrated circuit package capable of preventing illicit access by the execution of a program in an external memory.
To attain the above object, a processing apparatus according to the present invention is characterized by comprising:
an internal circuit, the internal circuit including a CPU executing a program; an internal memory storing an internal program; a bus line connecting the CPU to the internal memory, extending externally and transmitting an address and data; and a scramble section provided at an outlet and inlet of the bus line to an exterior and scrambling at least the data out of the address and the data on the bus line; and
an external memory provided exteriorly of an externally extending portion of the bus line and storing an external program, wherein
the internal circuit further includes an address controller monitoring whether the address on the bus line is an address in a predetermined address region while the program stored in the external memory is being executed, and notifying the CPU when detecting the address in the predetermined region.
The processing apparatus according to the present invention has the internal circuit which includes the address controller as stated above. Due to this, even if the program stored in, for example, the external memory is illicitly replaced by another program, important programs and data are stored in the predetermined address region and the CPU is notified when the address region is accessed from externally. This allows the CPU to take measures including invalidating the access in response to the notification, completely stopping the execution of the program stored in the external memory and notifying the exterior of the CPU of such illicit access.
In the processing apparatus according to the present invention, the CPU may typically prohibit access to the address detected by the address controller when notified by the address controller.
Further, in the processing apparatus according to the present invention, the internal memory may include an ROM; and the address controller may monitor whether the address on the bus line is an address in a part of address regions allotted to the ROM. In that case, the ROM preferably store an OS program in a part of the address region monitored by the address controller among the address regions allotted to the ROM.
The OS (operation system) program serves to control the overall processing apparatus and it is, therefore, quite significant that the OS program is not illicitly accessed.
Moreover, in a processing apparatus according to the present invention, it is preferable that the internal memory includes an ROM and an RAM; and the address controller monitors whether the address on the bus line is an address in at least a part of address regions allotted to the ROM and monitors whether the address on the bus line is an address in at least a part of address regions allotted to the RAM.
By doing so, it is possible to protect readable and writable data stored in the RAM from being illicitly accessed from externally.
Further, to attain the above object, an integrated circuit is characterized by being constituted by integrating, on one chip, a CPU executing a program; an internal memory storing an internal program; a bus line connecting the CPU to the internal memory, extending externally, having an externally extending portion of which an external memory storing an external program is provided exteriorly, and transmitting an address and data; a scramble section provided at an outlet and inlet of the bus line to an exterior and scrambling at least the data out of the address and the data on the bus line; and an address controller monitoring whether the address on the bus line is an address in a predetermined address region while the program stored in the external memory is being executed, and notifying the CPU when detecting the address in the predetermined region.
The integrated circuit according to the present invention has the above-stated constitution, provides the equivalent function and advantage to those of the processing apparatus according to the present invention. In addition, since the integrated circuit according to the present invention is mounted on one chip(LSI), it is difficult to inspect and examine the circuit arrangement or electric voltage output of the LSI without employing a high magnification microscope and a fine machining device. In this respect, too, the integrated circuit according to the present invention can prevent the interpretation and interpolation of data.
In the integrated circuit according to the present invention, the CPU may typically prohibit access to the address detected by the address controller when notified by the address controller as in the case of the above-stated processing apparatus according to the present invention.
Further, in the integrated circuit according to the present invention, the internal memory may includes an ROM; and the address controller may monitors whether the address on the bus line is an address in a part of address regions allotted to the ROM. In that case, the ROM preferably stores an OS program in a part of the address region monitored by the address controller among the address regions allotted to the ROM.
Moreover, in a processing apparatus according to the present invention, it is preferable that the internal memory includes an ROM and an RAM; and the address controller monitors whether the address on the bus line is an address in at least a part of address regions allotted to the ROM and monitors whether the address on the bus line is an address in at least a part of address regions allotted to the RAM.
Additionally, to attain the above object, an integrated circuit package according to the present invention is characterized by being constituted by integrating, on one chip, a CPU executing a program; an internal memory storing an internal program; a bus line connecting the CPU to the internal memory, extending externally, having an externally extending portion of which an external memory storing an external program is provided exteriorly, and transmitting an address and data; a scramble section provided at an outlet and inlet of the bus line to an exterior and scrambling at least the data out of the address and the data on the bus line; and an address controller monitoring whether the address on the bus line is an address in a predetermined address region while the program stored in the external memory is being executed, and notifying the CPU when detecting the address in the predetermined region and molding the one chip.
The integrated circuit package according to the present invention is constituted by molding the integrated circuit according to the present invention (LSI). Thus, in addition to the equivalent function and advantage to those of the LSI according to the present invention, it is possible to make it more difficult to contact with circuit parts such as the internal bus line by molding the circuit. It is almost impossible to inspect and examine the electric voltage output of the LSI. Besides, it is possible to further ensure preventing the interpretation and interpolation of internal data.